SW1-62A is master cell building block for analog switches and transmission gates. The cell consists of 12 NFETs and PFETs (6 of each type). For a given FET type, pairs of transistors are connected source to drain. These pairs share gate connections such that the 3 FETs with the free sources are connected together, as are the gates of the 3 FETs with the free drains. This topology allows a variety of switch configurations to be created. By design, total capacitance is identical for both NFET and PFET gate connections.
Each cell can be via-configured to be an NMOS, PMOS, complementary (transmission gate– NMOS and PMOS in parallel), NMOS only SPDT, PMOS only SPDT, complementary SPDT, NMOS only DPDT, PMOS only DPDT, or complementary DPDT switch. On-resistance is also via-configurable by paralleling more or less devices (PFET channel resistance is 3 times that of the NFET for a given transistor). This allows options for VCELLs with matched channel resistance or matched input capacitance.
Though intended for switch applications, the SW1-62A can also be used to create a variety of current mirror topologies for sinking and/or sourcing. Differential-pairs with current sources or active loads are also possible.
VCELL Table
| Name | # MCELLS Req | Description |
|---|---|---|
| vSPDT1-PX1-62A | 1 | SPDT PFET Switch (x1) |
| vSPDT1-PX2-62A | 1 | SPDT PFET Switch (x2) |
| vSPDT1-PX3-62A | 1 | SPDT PFET Switch (x3) |
