Index > Platforms > Configurable Tiles

Configurable Tiles

Configurable Tiles are groupings of non-configured Mcells, Collections, and/or Primitives that collectively perform a high-level function. A PLL tile, for example, contains the logic, oscillators, counters, and various primitives necessary to create the timing block for a large variety of possible designs.

Tile
Process Class
Circuit Category
Primary Content (Qty)
Switch/Mux (Qty)
Logic Cell (Qty)
Flipflop (Qty)
NFET/PFET (Qty)
Total Res/# of Dev's
Total Cap/# of Dev's
Other Content
VDD
ATMISC-7RF-101                      
ATCLKBUF-7RF-101                      
ATBIAS-7RF-101                      
ATRDAC-7RF-101                      
ATFD-7RF-101                      
ATSE-7RF-101                      
ATILE8-62A 62AMixed-SignalPOR (2), DAC (3)145422--1.2MΩ/31226.1pF/16S. E. Op Amp (2)3.3
AT6101                      
ATILE3-62A 62AAnalogBandgap (1)200--2.7MΩ/31214.4pF/8Start-Up Ckt (1),
NFET Mirrors (28),
PFET Mirros (92)		3.3
ATILE2-62A 62AAnalogS. E. Op Amp (2)2624124/242.0MΩ/31240.8pF/292--3.3
DTILE1-62A 62ADigitalSRAM (64 x 16 bits)1286464------Clk Buffs (324)3.3
ATILE7-62A 62AMixed-SignalPLL (1)1611228--24.1MΩ/312110pF/82NFET Mirrors (56),
PFET Mirros (66)		3.3
ATILE5-62A 62AAnalogProg. Resistor (var)1441440--5.1MΩ/576----
ATILE4-62A 62AAnalogBias Ckts (var)40540--2.0MΩ/31214.4pF/8NFET Mirrors (28),
PFET Mirros (92)		3.3
ATILE6-62A 62AAnalogDiff Op Amp (2)5248248/484.0MΩ/31281.6pF/584--3.3